In the present flat panel display technology, the liquid crystal display (LCD) technology is mature and has geometric growth every year in both the number of electronic products using the same and the number sold on the current market. Nevertheless, among all the LCDs, only the color and quality of the thin film transistor LCDs is good enough to compare with those of the cathode ray tube (CRT).
Today, many different processes for fabricating thin film transistor liquid crystal display (TFT LCD) have been developed. The conventional TFT LCD fabrication process primarily uses a deposition method to deposit a plurality of TFT structure layers onto a glass substrate in sequence. To accomplish a high-precision device and pixel arrangement, polysilicon has gradually replaced the amorphous silicon and has become a focus in the development of thin film transistor technologies.
However, the procedure of fabricating polysilicon devices generally requires the use of more than 9 masks for fabricating a polysilicon thin film transistor as disclosed in the U.S. Pat. No. 6,037,195, which is far more complicated and time-consuming than the 5 masks used for fabricating a typical amorphous silicon devices.
Thus, the U.S. Pat. No. 5,913,113 disclosed a fabrication process of 5 masks in order to lower the cost of manufacturing thin film transistor arrays. Although the 5 masks fabrication process of the U.S. Pat. No. 5,913,113 can save the amount of masks required, the most difficult technical issue of the foregoing patent resides on simultaneously etching dielectric layers with different depths causing a narrow process window unfavorable to the actual mass production. In addition, as disclosed in the patent, the process window is further restricted since the wiring process is occurs prior to the laser crystallization process.
In view of the description above, the conventional fabrication process of polysilicon thin film transistor has at least the following drawbacks:                1. The process is more complicated and time consuming since more masks are required to be used in the fabrication process of a conventional polysilicon thin film transistor, such that the manufacturing cost is increased and thus the competitiveness is negatively affected.        2. The prior-art fabrication process for producing a polysilicon thin film transistor etches the dielectric layers with different depths simultaneously causing a narrow process window that is unfavorable to actual mass production.        3. In the prior-art fabrication process for producing a polysilicon thin film transistor, the process window is further restricted, thus increasing the level of complexity of the overall fabrication process since the wiring process is occurs prior to the laser crystallization process.        